1. Field of the Invention
The present invention generally relates to a nonvolatile semiconductor memory device, and particularly relates to a nonvolatile semiconductor memory device adapted to erase data on a whole sector at a time.
2. Description of the Related Art
Nonvolatile semiconductor memory devices are designed to write data by a programming operation of injecting charges into a gate of a memory cell transistor, and to erase data by an erasing operation of removing charges from the gate of the memory cell transistor. The programming and erasing operations are executed by applying a voltage predetermined for each operation to respective terminals of the gate, the drain and the source of the memory cell transistor. The predetermined voltage must be a voltage higher than an external supply voltage supplied from the outside or a negative voltage lower than a ground voltage. The nonvolatile semiconductor memory devices therefore include internal program voltage and erase voltage generating circuits to generate a high voltage and a negative voltage.
In word line voltage control, the high voltage for programming generated by the program voltage generating circuit is applied to a selected word line in a selected sector via an X-decoder circuit. The negative voltage for erasure generated by the erase voltage generating circuit is applied to word lines in a selected sector via the X-decoder circuit.
FIG. 1 is a schematic diagram of an X-decoder circuit. This X-decoder circuit is provided one for each block. If there are plural blocks, that same number of X-decoder circuits of FIG. 1 are provided. The X-decoder circuit is configured to be connected to plural sectors. (e.g. sectors S1, S2 in FIG. 1).
The X-decoder circuit of FIG. 1 includes a high-voltage switching circuit 11, a global X-decoder 12, high-voltage X-decoders 13, sub X-decoders (word line drives) 14, and sector switches 15. The high-voltage switching circuit 11 and the global X-decoder 12 are shared by the plural sectors. The high-voltage X-decoder 13, plural sub X decoders 14, and the sector switch 15 are respectively provided in each of the plural sectors.
FIG. 2 is a circuit diagram of the high-voltage switching circuit 11.
The high-voltage switching circuit 11 of FIG. 2 includes AND circuits 21 and 22, an OR circuit 23, NMOS transistors 24 through 26, and PMOS transistors 27 through 29. A signal SELq is a signal for selecting a corresponding block, and a signal SELBq is an inversion signal of the signal SELq. A signal ERSELVT is normally LOW (ground voltage Vss), and becomes HIGH (supply voltage Vcc) in the erase operation. A signal ERSELBVT is normally HIGH (supply voltage Vcc), and becomes LOW (ground voltage Vss) in the erase operation. A signal SVPX becomes HIGH in the read/program operation. VPXG is an input high voltage.
The output voltage VPXq applied to a block selected for the read/program operation is the input high voltage VPXG, because SVPX=H, SELq=H, and ERSELVT=L. On the other hand, the output voltage VPXq applied to a block unselected for the read/program operation is the ERSELBVT, because SVPX=H, and SELq=L. The voltage ERSELBVT is Vcc in the read operation.
The output voltage VPXq applied to a block selected for the erase operation is 0 V, because ERSELVT=H, and SVPX=L. On the other hand, the output voltage VPXq=VPXG=Vcc is applied to a block unselected for the erase operation.
FIG. 3 is a circuit diagram of the global X-decoder 12.
The global X-decoder 12 of FIG. 3 includes NAND circuits 31 and 32, inverters 33 and 34, NMOS transistors 35 and 36, and PMOS transistors 37 and 38. The global X-decoder 12 applies GWLNqx=VPXq, and GWLBqx=0 V to a block selected for the read/program operation. On the other hand, the global X-decoder 12 applies GWLNqx=0 V, and GWLBqx=Vcc to a block unselected for the read/program operation. The output signals GWLNqx and GWLBqx are globally applied to the sectors. In the erase operation, VPXq=0 V, ERXTFB=0 V, and XTx=0 V, and therefore GWLNqx=0 V, and GWLBqx=0 V.
Thirty two pieces of the circuits of FIG. 3 are respectively provided for 32 lines of GWLNq (31:0) and GWLBq (31:0). The global X-decoder 12 is constituted with all these circuits (see FIG. 1). The GWLNqx and GWLBqx described above respectively correspond to single lines of GWLNq (31:0) and GWLBq (31:0).
FIG. 4 is a circuit diagram of the high-voltage X-decoder 13.
The high-voltage X-decoder 13 of FIG. 4 includes a NAND circuit 41, NMOS transistors 42 and 43, and PMOS transistors 44 and 45. The PMOS transistors 44 and 45 serve as a level shifter for converting logic in Vcc level into logic in Vpx level. A signal ERXTFB becomes LOW and sets a pass gate OFF in the erase operation. A signal VXTv, which is a signal converted from an address signal, becomes HIGH when a corresponding VWL is selected for the decoding operation. A signal SELn becomes HIGH when a sector is selected. XDS, which is a voltage signal, is normally 0 V and becomes a negative voltage NEGP (e.g. −6 V) in the erase operation.
When the read/program operation is selected, VWLnv=VPXq. When the read/program operation is unselected, VWLnv=0 V. In the erase operation, VPXq=0 V, VXTv=SELn=H, and XDSn=NEGP, and therefore VWLnv=NEGP. Herein, NEGP is a negative voltage in the erase operation as shown in the above.
Sixteen pieces of the circuits of FIG. 4 are respectively provided for 16 lines of VWLn (15:0). The high-voltage X-decoder 13 is constituted with all these circuits (see FIG. 1). The VWLnv of FIG. 4 described above corresponds to a single line of VWLn (15:0). The high-voltage X-decoder 13 is provided one for each sector.
FIG. 5 is a circuit diagram of the sub X-decoder 14.
The sub X-decoder (word line driver) 14 of FIG. 5 includes NMOS transistors 51 through 53. The sub X-decoder 14 receives VWLnv from the high-voltage X-decoder 13, VPXq from the high-voltage switching circuit 11, GWLNqx and GWLBqx from the global X-decoder 12, and XDSn from the sector switch 15. According to these signals, the sub X-decoder 14, serving as a word line driver, drives a word line.
When a word line is selected for the read/program operation, GWLNqx=VPXq, GWLBqx=0 V, and VWLnv=VPXq. Therefore, a high voltage is applied to a word line P2WLni. When a word line is selected for the erase operation, VPXq=0 V, VWLnv=XDSn=NEGP, and GWLNqx=GWLBqx=0 V. Therefore, a negative voltage NEGP is applied to the word line P2WLni.
FIG. 6 is a circuit diagram of the sector switch 15.
The sector switch 15 of FIG. 6 includes NAND circuits 61 and 62, inverters 63 and 64, NMOS transistors 65 through 71, and PMOS transistors 72 through 77. A signal ENSSW is an Enable signal for this circuit. A signal SELn is a sector selection signal as previously mentioned. NEGP is a negative voltage supplied from a pump circuit. A signal NEGPL is a negative voltage detection signal, which is switched from Vcc to 0 V when the negative voltage signal NEGP falls below a predetermined negative voltage level.
An output voltage signal XDSn is a negative voltage when in a selected sector, and is 0 V when in an unselected sector. Specifically, in the selected sector, signals AEN and NEN in the circuit are respectively NEGP and 0 V, and therefore the output voltage signal XDSn=NEGP. In the unselected sector, signals AEN and NEN are respectively Vcc and NEGP, and therefore XDSn=0 V.
The sector switch 15, provided one for each sector, supplies a negative voltage for erasure to the sub X-decoders 14 when a corresponding sector is selected for the erase operation. Thus the erase operation is executed in the sector.
The high-voltage switching circuit 11 shown in FIG. 2 is shared by the sectors, thereby allowing a reduction of the circuit area. The reason that the sharing of the high-voltage switching circuit 11 is applicable is because the word line can be selected by the decoding operation of GWL/VWL in the read/program operation.
In contrast, the sector switch 15 shown in FIG. 6 is provided one for each sector. The size of the sector switch 15 is large because the sector switch 15 includes a level shifter for controlling a negative voltage to be applied to a selected sector and a decoding circuit for generating the signals AEN and NEN. Therefore, having the sector switch 15 one for each sector is disadvantageous in that the circuit area occupied by the sector switches 15 increases in proportion to the number of the sectors (an example of related art is described in U.S. Pat. No. 5,995,417, also published as WO00/24002, and its Japanese translation 2002-528841).